It is well known and often quoted that unpredictability of load latency is a major problem of the itanium architecture. free netflix I wonder if i understand this correctly:
In an out of order core, there are certain later instructions that are independent of the load instruction and these can be executed out of order. For example there can be a group of instructions that depend on an unrelated load (which turned out to be a cache hit) and these can be executed in the OOO CPU, but not in the in-order itanium CPU.
Is this the main issue that is referred to as “the compiler cannot compensate for the architectural weakness”? tech news What other issues can be added to this list of definite advantages of the running CPU versus the static view of the compiler?